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Search - 8 BIT SHIFT REGISTER VHDL

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[Other resource] spi

Description: VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the \"master\" and the \"slave\". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.
Platform: | Size: 65393 | Author: 阿飞 | Hits:

[Communication-Mobile] iic_vhdl

Description: iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- post-route I2C simulation netlist
Platform: | Size: 889991 | Author: benny | Hits:

[VHDL-FPGA-Verilog] spi

Description: VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
Platform: | Size: 65536 | Author: 阿飞 | Hits:

[Other] shift8

Description: 8 位移位寄存器 VHDL程序 VHDL程序 VHDL程序-8-bit shift register VHDL procedures VHDL procedures VHDL procedures
Platform: | Size: 197632 | Author: 周辉 | Hits:

[Communication-Mobile] iic_vhdl

Description: iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- post-route I2C simulation netlist -IIC bus controller VHDL realize- VHDL Source Files: i2c.vhd- top level file i2c_control.vhd- control function for the I2C master/slave shift.vhd- shift register uc_interface.vhd- uC interface function for an 8-bit 68000-like uC upcnt4.vhd- 4-bit up counter i2c_timesim.vhd- post-route I2C simulation netlist
Platform: | Size: 889856 | Author: benny | Hits:

[VHDL-FPGA-Verilog] shifter

Description: 8位双向移位寄存器: 实现串行数据与并行数据的转换,移位寄存数据功能的-8-bit bi-directional shift register: the realization of serial data and parallel data conversion, data storage function of displacement
Platform: | Size: 45056 | Author: 罗子 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 74ls164 8位移位寄存器 串入并出-74ls164 8-bit shift register and a string into
Platform: | Size: 1024 | Author: fankexing | Hits:

[VHDL-FPGA-Verilog] left_shift_register

Description: 用ＥＤＡ实现的一个带有同步并行预置功能的８位左移移位寄存器-With the EDA to achieve a preset function in parallel with synchronous 8-bit left shift register
Platform: | Size: 147456 | Author: 哈哈 | Hits:

[VHDL-FPGA-Verilog] 8-bitinput-output-shift

Description: 8位串行输入，串行输出移位寄存器 VHDL-8-bit serial input, serial output shift register VHDL
Platform: | Size: 1024 | Author: LT | Hits:

[VHDL-FPGA-Verilog] VHDL-test-code-8-bit-shift-register

Description: VHDL实验代码：8位移位寄存器，这是一个基于VHDL的8位寄存器，非常实用的一个小程序-VHDL test code: 8-bit shift register, which is a VHDL-based 8-bit registers, a very useful little program
Platform: | Size: 1024 | Author: Johonson | Hits:

[VHDL-FPGA-Verilog] multi8x8

Description: 该源码为8位乘法器的VHDL语言描述，由一个8位右移寄存器，2个4位加法器例化成8位加法器，一个16位数据锁存器构成。采用移位相加的方式，从被乘数的低位开始，与乘数的每个位移位相加求和。最后实现其乘法器功能。-The source code for the 8-bit multiplier in VHDL language to describe, from an 8-bit right shift register, two 4-bit adder example into 8-bit adder, a 16-bit data latch form. Using the sum of the shift, from a low starting multiplicand, the multiplier for each bit shift and summed. Finally, to achieve its multiplier function.
Platform: | Size: 393216 | Author: feng | Hits:

[VHDL-FPGA-Verilog] Shfit8bit

Description: 8位移位寄存器的vhdl设计，经过仿真验证，程序简单易懂，易于初学者借鉴-8-bit shift register vhdl design, through simulation, the program is easy to understand, easy for beginners learn from
Platform: | Size: 1024 | Author: 王龙飞 | Hits:

[VHDL-FPGA-Verilog] shift8

Description: 完成8位移位寄存器的VHDL设计、仿真、下载验证，要求有带进位循环右移、带进位循环左移、自循环右移和自循环左移功能。-Completed the 8-bit shift register VHDL design, simulation, download authentication, and require Rotate right, Rotate left, since the rotate right and left from the circulation function.
Platform: | Size: 290816 | Author: 沈桑霞 | Hits:

[VHDL-FPGA-Verilog] an-8-bit-left-shift-register

Description: 使用VHDL语言设计一个8 位左移移位寄存器。并给出了仿真波形。-Using VHDL to design an 8-bit left shift register. And simulation waveforms.
Platform: | Size: 2048 | Author: clementkv | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: VHDL初级编程实例：动态扫描显示程序、分频器设计程序、8位移位寄存器、BCD计数器设计(任意进制)等等。-VHDL the primary programming examples: dynamic scanning display program, the divider design process, the 8-bit shift register, BCD counter design (any hex), and so on.
Platform: | Size: 11264 | Author: 罗梵 | Hits:

[VHDL-FPGA-Verilog] ShiftRegs

Description: i am uploading the vhdl code for a 8 bit shift register
Platform: | Size: 15360 | Author: sandeep | Hits:

[Com Port] SPI_verlog

Description: VHDL 语言实现的串转并 SPI 等等 实现-The SPI bus is a 3 wire bus that in effect links a serial shift-- register between the master and the slave . Typically both the-- master and slave have an 8 bit shift register so the combined-- register is 16 bits. When an SPI transfer takes place, the master and-- slave shift their shift registers 8 bits and thus exchange their 8-- bit register values.
Platform: | Size: 1024 | Author: 向东 | Hits:

[Other] 2

Description: 用VHDL语言设计一个8位双向可控移位寄存器。 移位寄存器由D型触发器构成，采用串入并出形式。 采用VHDL方式设计一个16х4位RAM存储器-VHDL language to design an 8-bit bidirectional shift register controllable. The shift register by a D-type flip-flops, using the string into and out of form. Way design using VHDL a bit RAM memory 16х4
Platform: | Size: 1024 | Author: 赵丽丽 | Hits:

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